The present invention relates to a semiconductor integrated circuit device, more particularly to a technique for preventing the device from malfunction when its IC chip cracks.
Recently, xe2x80x9cIC cardsxe2x80x9d each of which employs a semiconductor integrated circuit device, have come into widespread use. An IC card has various functions equivalent to those realized by a magnetic card at present, for example, exchanging data with a reader/writer through the semiconductor integrated circuit device mounted thereon.
Some IC cards are protected from chip cracks with the use of various techniques, to thicken the IC card itself in structure for avoiding a stress to be applied onto the chip thereof, to compose the IC card so as to avoid a stress to be applied onto the chip itself, and/or to reinforce the chip with a board.
Along with the popularization of the IC cards, a demand for thinner IC cards is increasing. This also creates the demand for thinner IC chips used in the IC card, and a problem that the chips become weak in shock resistance and tend to be easily cracked. Although the circuits of an IC card are in disabled condition when the chip is cracked, still a problem will arise. There is the problem of malfunction of the chip, caused by the coexistence of active and inactive circuits under the cracked chip.
In particular, an IC chip is often mounted on an IC card so as to come in close contact with the principal part of the card. So, unlike a case in which the chip is pinned on a board, a part of the chip continues an imperfect operation even after the chip is cracked. Concretely, the chip used as a single unit is cracked to pieces, then the chip will be disabled for operation. The chip used as a part of an IC card, however, might continue its operation on the cracked chip. Imperfect operation of the chip due to this is serious problem especially in the use of the IC card for security and cashing.
Under the circumstances, the present invention aims to provide a semiconductor integrated circuit device that never malfunctions when the chip is cracked.
The Japanese Patent Laid-Open No. 6-244254 discloses a technique for detecting defective chips including circuit element cracks. In the technique, a conductor pattern is formed on the surface of a circuit element, then a pad for measurement is formed on this pattern. Then, the resistance variation of the pattern is measured from outside, thereby selecting defective chips.
This technique is intended to select defective chips, not intended for detecting chips cracked after shipping. In the case of an IC card to which the present invention is expected to be applied, the chip is often damaged in actual practice. The present invention, thus, aims to surely avoid a chip malfunction caused by the cracked chip brought about in actual practice.